The FT-U Project
FT-U Board
FT-UNSHADES is a version of the UNSHADES concept dedicated to study Fault Tolerant Circuits and the measurement of the robustness of a netlist against soft errors. It's based on the propietary method for inserting controlled modifications into the current state of the emulator device (VirtexII, XC2V4000, XC2V6000, xC2V8000) during execution time. Using this board and software, fault tolerance detailed analysis can be produced before IC fabrication
Ariane
The project was designed and engineered by a team of researchers from the Electronics Engineering Dept. of the University of Seville under contract with the European Space Agency (Microelectronics Section), the University of Seville and AICIA (Contract No. 17540)
Brief Description
FT-UNSHADES is a platform based on Xilinx Virtex series FPGAs. It is a version of the UNSHADES hardware and software co-design and co-debug system, intended for fault injection test.
| Milestones | Date |
|---|---|
| Project finished | Sept. 2004 |
| LEON2 extension | May 2005 |
| Presentation in MAPLD (Washington DC, USA) | Sept. 2005 |
| FT-Usb becomes operative for radiation tests | Jan. 2006 |
| Publication in the IEEE Transactions on Nuclear Science | Aug. 2007 |
| FT-U 2 starting point | Jan. 2009 |
FT-UNSHADES is based on a dedicated hardware platform and a specific software tool devoted to the control of the test injection campaign.
The hardware platform is based on two FPGAs. The first one, called Control FPGA or CFPGA, provides communication between the hardware platform and the system host. The second one, called System FPGA or SFPGA (a Xilinx XC2V8000 device in the current version of FT-UNSHADES), hosts the system under test. In addition three 24MB SRAM memories store the input stimuli database.
In the software side, a system framework has been developed using a simple test language which defines the test injection campaign and helps in the analysis of the results. After a fault injection campaign, a fault database is produced containing the necessary information to analyze the fault activity. In addition, the designer can select a step-by-step execution of one of the experiments stored in the fault database, making possible a detailed analysis of how the injected fault propagates through the circuit.
The circuit to be tested is prepared using software routines integrated into the Xilinx standard design flow. Three actions are required:
- Test vectors are obtained from an HDL simulator. Then they are properly formatted and compressed.
- The circuit to be emulated is synthesized using the Xilinx Virtex II design flow to obtain the Module Under Test (MUT) using any synthesis tool. After synthesis, formal verification checks should be performed in order to guarantee RTL matching between Xilinx and ASIC vendor netlists.
- The MUT is encapsulated to build the so-called Design for Test Emulation (DTE).
The structure of a DTE is made up of two identical copies of the MUT (named Gold and Faulty, respectively) which are instantiated along with a control unit called Test Shell. During the fault injection campaign a comparator will detect discrepancies (if any) between the corresponding outputs at the Gold and Faulty instances. Then, the DTE is downloaded on the SFPGA, to start the emulation.
The Test Shell is a simple hardware which performs four tasks:
- It loads the stimuli database to the internal SRAM memories of the FT-UNSHADES hardware platform.
- It decompresses the stimuli from the internal SRAM memories.
- Once the emulation process stars, it controls the emulation clock to determine the time of fault injection, then injects the fault and allows a cycle-by-cycle propagation of the fault until a discrepancy is observed between the corresponding outputs of the Gold and Faulty instances, or until the stimuli vector is exhausted.
- Finally, at every time, it controls the dialog between the FT-UNSHADES platform and the host.
Read more about FT-U
If you feel you need to know more about FT-UNSHADES and other related projects, take a look to the Publications link where we list our scientific papers about the effects of radiation in electronics
Basic Example
The next message corresponds to a simple fault injection test performed over the LEON2 processor:
#RUN 1 Selected clk cycle for SEU insertion: 133937 Selected reg for SEU insertion: SEU_MUT/leon0_mcore0_proc0_cx.c0_icache0_r.waddress_16 OK Output error detected in port: address Damage detected 1 clk cycle after SEU insertion Total elapsed time: 0.06251 Target size: 1, registers Total FPGA cycles: 0x0,00020B32 <133938>
In this output message, one can see the clk cycle selected to inject the bit-flip (133937) and the target register (leon0_mcore0_proc0_cx.c0_icache0_r.waddress_16). If damage is detected, the system record the port affected and the time when the fault appeared.
